MCP6S92-E/SN

Overview

The MCP6S92-E/SN is a single-supply, dual-channel analog Programmable Gain Amplifier (PGA) from Microchip Technology. It features an integrated input multiplexer selectable via a Serial Peripheral Interface (SPI). The device supports eight discrete gain settings ranging from +1 V/V to +32 V/V. It operates on a single supply voltage between 2.5V and 5.5V with rail-to-rail input and output capabilities. Key electrical characteristics include a maximum DC gain error of ±1%, zero offset mismatch between channels, and a typical quiescent current of 1.0 mA.

Feature Summary

• Integrated SPI-controlled multiplexer for selecting between two analog input channels
• Rail-to-rail input and output operation compatible with single-supply systems
• Low DC gain error ensuring high signal accuracy across the gain range
• Zero offset voltage mismatch between the two internal amplifier channels

Applications

• A/D Converter Driver
• Multiplexed Analog Applications
• Data Acquisition Systems
• Industrial Instrumentation
• Medical Instrumentation

Procurement Notes

Verify that the ordering suffix 'SN' corresponds to the SOIC-8 package type required by your PCB layout. Confirm the '-E' designation indicates the extended temperature range specification (-40°C to +125°C). Ensure the design accommodates the specific pinout for the MCP6S92 variant, particularly regarding the internal connection of the VREF pin to VSS.

Selection Notes

Select this component when a system requires flexible gain adjustment for multiple analog inputs without external resistor networks. It is suitable for applications needing low offset drift and high bandwidth relative to the gain setting. Consider the power consumption profile if battery operation is critical, noting the shutdown mode capability via the SPI interface.

Part Context

This part belongs to the MCP6S91/2/3 family of single-ended, rail-to-rail, low-gain PGAs. The MCP6S92 specifically provides two input channels, distinguishing it from the single-channel MCP6S91 and the ten-pin MCP6S93. All variants share identical core performance specifications and SPI control logic.

Replacement Considerations

MCP6S91-E/SN: Single-channel version with identical electrical specs.

FAQ

How is the VREF pin handled in the MCP6S92?

In the MCP6S92, the VREF pin is tied internally to VSS. This configuration means the Power Supply Rejection Ratio (PSRR) specification describes PSRR+ only.

What is the input offset voltage mismatch between channels?

The input offset voltage mismatch between the CH0 and CH1 channels is ideally 0 µV, as the internal multiplexer uses CMOS transmission gates without inherent offset voltage.