MK1575-01G

Overview

The MK1575-01G is a clock recovery Phase-Locked Loop (PLL) designed for cost-sensitive video and telecom applications. It synthesizes high-frequency data or graphics pixel clocks from low-frequency reference inputs. The device operates on a single 3.3V supply (3.15V to 3.45V) with an operating temperature range of 0°C to 70°C. It features one circuit with a 1:2 input-to-output ratio, delivering LVCMOS outputs at frequencies up to 80MHz. Packaged in a 16-TSSOP case, it includes selectable internal feedback dividers for standard telecom and video frequencies.

Feature Summary

• Long-term output jitter less than 2 nsec over a 10 µsec period
• External PLL clock feedback path enables zero-delay I/O clock skew configuration
• Selectable internal feedback divider supports standard telecom and video clock frequencies
• Single 3.3V supply with power-down mode and output tri-state capability

Applications

• Video clock synthesis and synchronization
• Telecom T/E clock modes
• Graphics pixel clock generation

Procurement Notes

Verify the specific suffix against the ordering information table to confirm packaging and temperature grade. The 'G' suffix indicates the commercial temperature range (0 to +70 °C). Packaging options include tubes ('') or tape and reel ('TR'). Ensure the required variant matches the application's thermal and handling specifications.

Selection Notes

Select based on the required frequency combination and temperature range. Use the Detailed Mode Selection Table to determine the correct FS2:0 address bits for the desired input/output frequency pair. For video genlock, a loop bandwidth of 700 Hz and damping factor of 0.7 is typical. External loop filter components must be selected to tailor the loop response and minimize jitter.

Part Context

This component belongs to the IDT Clock Recovery PLL series, now manufactured by Renesas Electronics Corporation following acquisitions. The MK1575-01 is optimized for cost-sensitive applications requiring clock synthesis from low-frequency references. It serves as a solution for generating precise timing signals in video and telecommunications infrastructure.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. The datasheet notes that EOL for non-green parts occurred on 5/13/10. Verify if the LF-suffixed variants (e.g., MK1575-01GLF) are suitable replacements for lead-free requirements within the same package and temperature range.

FAQ

How is the zero-delay buffer configuration achieved?

Zero-delay I/O clock skew is configured by connecting the external PLL clock feedback path directly to either CLK1 or CLK2, depending on the specific application requirements.

What is the function of the OE pin?

The OE (Output Enable) pin tristates the CLK1, CLK2, and FCLK outputs when held high. Additionally, holding OE high powers down the PLL.

Can the device generate frequencies other than the pre-configured ones?

Yes, while it has selectable internal feedback dividers for popular frequencies, it can optionally use an external feedback divider to generate other output frequencies.