MK1575-01GI

Overview

The MK1575-01GI is a clock recovery Phase-Locked Loop (PLL) designed for cost-sensitive video and telecom applications. It synthesizes high-frequency data or graphics pixel clocks from low-frequency reference inputs. The device operates on a single 3.3V supply with a voltage range of 3.15V to 3.45V, consuming 10mA at typical conditions. It features LVCMOS outputs and supports a maximum output frequency of 80MHz. Packaged in a 16-TSSOP, it includes selectable internal feedback dividers for standard frequencies and allows external loop filter customization for specific jitter and bandwidth requirements.

Feature Summary

• Long-term output jitter less than 2 nsec over a 10 µsec period
• External PLL clock feedback path enables zero-delay I/O clock skew configuration
• Selectable internal feedback divider provides pre-configured telecom and video clock frequencies
• Single 3.3V supply with power-down mode and output tri-state capability

Applications

• Video genlock and synchronization
• Telecom T/E clock synthesis
• Graphics pixel clock generation

Procurement Notes

Verify the 'GI' suffix indicates the industrial temperature grade (-40°C to +85°C). Confirm RoHS compliance status as non-green parts have reached End-of-Life. Check current availability through authorized distributors since original manufacturer IDT was acquired by Renesas.

Selection Notes

Select this component when low-cost clock synthesis from low-frequency references is required. Ensure external loop filter components are chosen to meet specific damping factor and bandwidth needs for the application. Verify that the 80MHz maximum output frequency meets system requirements.

Part Context

This part belongs to the MK1575-01 family of clock recovery PLLs. The 'GI' suffix specifically denotes the industrial temperature range variant packaged in tubes. Other variants include commercial temperature ranges and lead-free options.

Replacement Considerations

Direct replacements may be limited due to EOL status. Consider the MK2069 for lower jitter requirements or verify if other Renesas/IDT clock synthesizers support similar pinouts and frequency ranges.

FAQ

What is the function of the OE pin?

The OE pin acts as an Output Enable. When held high, it tristates the CLK1, CLK2, and FCLK outputs and powers down the PLL.

How is the loop bandwidth adjusted?

Loop bandwidth is adjusted using external components connected to the CHGP and CHPR pins, specifically the resistor (RS) and capacitor (CS).

Can the device operate without an external feedback divider?

Yes, connecting FCLK to FBIN is the standard configuration for pre-configured frequencies without an external divider. Connecting CLK1 or CLK2 to FBIN creates a zero-delay buffer configuration.