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MM74HC164MTCX is listed in the Shift Registers range at ChipApex. The manufacturer field lists Fairchild Semiconductor. Its product description is SERIAL IN PARALLEL OUT, HC/UH SE. Review the specifications below when checking this part for your BOM.
The MM74HC164MTCX is an 8-bit serial-in parallel-out shift register manufactured by Fairchild Semiconductor, part of the 74HC logic series. It operates on a single supply voltage ranging from 2V to 6V and features push-pull outputs. The device is housed in a 14-TSSOP surface-mount package with a width of 4.40mm. It supports data shifting on the rising edge of the clock pulse and includes an asynchronous master reset input that forces all outputs low when active. The component functions as a single element with eight bits per element.
Verify the manufacturer designation, as this specific part number is frequently associated with onsemi production under the same base model. Confirm the package type matches the required 14-TSSOP footprint and ensure the supply voltage range aligns with system requirements. Check RoHS compliance status and moisture sensitivity level before integration into the assembly process.
Select this component when a non-inverting 8-bit shift register with parallel outputs is required within a 2V to 6V operating range. It serves as a direct replacement for other 74HC164 variants in TSSOP packages. Ensure the design accommodates the asynchronous reset behavior and utilizes the dual serial inputs effectively for data gating.
This device belongs to the 74HC family of high-speed CMOS logic, offering performance compatible with Low-power Schottky TTL (LSTTL) standards. It follows JEDEC standard no. 7A specifications. The MM74HC164MTCX variant specifically denotes the surface-mount TSSOP packaging option, distinguishing it from through-hole or SOIC versions within the same logical family.
MC74HC164ADTR2G
When the master reset input is held at a low logic level, it ignores all other inputs and immediately forces all eight outputs to a low state.
Data shifts to the right on each rising edge of the clock pulse, with the new bit entering based on the logical AND of the two serial data inputs.
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