MPC8347ECVRAGDB

Overview

The MPC8347ECVRAGDB is a PowerQUICC II Pro integrated host processor based on the e300 core. It features a 32-bit architecture with up to 667 MHz operation, 32 KB instruction and data caches, and DDR1/DDR2 memory support. The device integrates dual Gigabit Ethernet controllers, PCI interfaces, USB 2.0, and a security engine for encryption algorithms.

Feature Summary

• Integrated e300 superscalar processor core with floating-point capabilities
• Dual three-speed Ethernet controllers supporting IEEE standards
• Hardware security engine for IPSec, SSL/TLS, and RAID acceleration
• USB dual-role controller compatible with USB 2.0 specifications

Applications

• Ethernet routers and switches
• Wireless LAN (WLAN) devices
• Network storage systems
• Industrial control equipment

Procurement Notes

Verify silicon revision level before procurement; this document applies to revision 3.x silicon and later. Confirm package type compatibility as specifications vary between PBGA and TBGA variants. Check for updated errata or product summaries on official channels prior to design finalization.

Selection Notes

Select based on required clock frequency and I/O voltage levels. Ensure power sequencing adheres to core voltage application before I/O supplies to prevent contention. Verify memory interface requirements against supported DDR1 or DDR2 configurations.

Part Context

Part of the PowerQUICC II Pro family designed for networking and embedded applications. Built on Power Architecture technology, it offers software compatibility with other Freescale processor families while providing enhanced performance through the e300 core and integrated peripherals.

Replacement Considerations

NXP recommends using Power Architecture T1013 or Arm Architecture LS1012 and LS1023 families for new designs.