MPC8347ZQADDB

Overview

The MPC8347ZQADDB is a PowerQUICC II Pro integrated host processor based on the e300 core. It features a 32-bit superscalar architecture with 32 KB instruction and data caches, operating up to 667 MHz. The device includes dual 10/100/1000 Ethernet controllers, a PCI interface, USB 2.0 multi-port host controller, DDR SDRAM memory controller, and an integrated security engine supporting DES, AES, and RSA algorithms.

Feature Summary

• Integrated security engine for hardware-accelerated encryption and authentication
• Dual three-speed Ethernet controllers for network connectivity
• DDR SDRAM memory controller with ECC support
• USB 2.0 multi-port host controller functionality

Applications

• Network routers and switches
• Wireless LAN devices
• Network storage systems
• Industrial control equipment

Procurement Notes

Verify silicon revision compatibility before integration. This document covers revision 1.1 silicon and earlier; newer revisions require separate specifications. Confirm package type and voltage requirements match design constraints. Check for updated errata or product change notices prior to finalizing procurement plans.

Selection Notes

Select this component for applications requiring high-performance embedded processing with integrated networking and security features. Ensure system design accommodates specific I/O voltage levels and power dissipation characteristics. Verify software compatibility with existing Power Architecture implementations.

Part Context

Part of the PowerQUICC II Pro family designed for cost-effective, highly integrated communication solutions. Based on the e300 SoC platform, it offers enhanced performance over previous generations while maintaining software compatibility. Targeted at emerging network and computing markets.

Replacement Considerations

Consult NXP for current replacement families such as Power Architecture T1013 or Arm Architecture LS1012/LS1023.