MPC8349EZUAJF

Overview

The MPC8349EZUAJF is a PowerQUICC II Pro integrated host processor built on the e300 core. It operates at up to 667 MHz with 32-Kbyte instruction and data caches. The device features dual three-speed Ethernet controllers, dual PCI interfaces, and DDR1/DDR2 memory support up to 400 MHz. Integrated security engines handle encryption algorithms, while USB controllers provide high-speed connectivity.

Feature Summary

• Integrated e300 superscalar processor core with floating-point capabilities
• Dual three-speed Ethernet controllers supporting multiple physical interfaces
• Integrated security engine for hardware-accelerated cryptographic processing
• Support for DDR1 and DDR2 SDRAM with ECC capability

Applications

• Enterprise networking equipment
• Telecom transmission and switching systems
• Industrial control devices
• Network storage solutions

Procurement Notes

Verify silicon revision level before procurement; this document applies to revision 3.x silicon and later (orderable part numbers ending in A or B). Confirm voltage requirements match system design, specifically core supply tracking with I/O supplies. Ensure proper power sequencing during implementation to avoid excessive current draw.

Selection Notes

Select this component for applications requiring high-performance embedded processing with integrated networking peripherals. Consider the e300 core's software compatibility with other Power Architecture families. Evaluate thermal dissipation requirements based on operating frequency and load conditions specified in the power characteristics section.

Part Context

This processor belongs to the PowerQUICC II Pro family, designed for communications processing. It builds upon previous generations by offering enhanced performance through the e300 core and increased integration of high-speed interfaces like Ethernet and PCI within a single system-on-chip architecture.

Replacement Considerations

Consult official documentation for compatible upgrades within the PowerQUICC series. Verify pinout and register compatibility when transitioning between different revisions or model variants.