MPC905DR2

Clock Buffers, Drivers Overview

The MPC905 is a six-output clock generation and fanout buffer device designed for PCI bus environments operating at 3.3V or 5.0V. It accepts an external crystal or TTL-compatible clock input and generates six low-skew LVCMOS outputs (BCLK0–BCLK5). The device operates from a 3.3V supply with 5.0V tolerant inputs, supporting maximum frequencies of 50 MHz with crystals and 100 MHz with external sources. Each output can drive up to two series-terminated 50 Ω transmission lines, providing a 1:12 fanout capability.

Clock Buffers, Drivers Feature Summary

• Six low-skew LVCMOS clock outputs (BCLK0–BCLK5) with output-to-output skew of 400 ps rising and 500 ps falling.
• Two synchronous enable inputs (Enable1, Enable2) for power management; Enable1 controls BCLK0–BCLK4, while Enable2 controls BCLK5.
• Integrated XTAL oscillator interface supporting fundamental and third overtone modes with specific capacitor requirements.
• 5.0V tolerant inputs allowing operation in mixed-voltage systems while maintaining a 3.3V supply.

Clock Buffers, Drivers Applications

• PCI bus clock distribution networks requiring low skew and high fanout.
• Processor bus clock generation in 3.3V or 5.0V environments.
• Systems requiring synchronized power management via hardware enable signals.

Clock Buffers, Drivers Procurement Notes

Verify the package suffix 'D' corresponds to the 16-lead Plastic SOIC (Case 751B-05). Confirm the operating temperature range matches the application requirements, as the datasheet specifies 0°C to +70°C. Ensure the supply voltage remains within the functional range of 3.0V to 3.6V. Check for any ordering suffixes that may indicate tape-and-reel packaging versus tubes, though the document primarily references the D suffix.

Clock Buffers, Drivers Selection Notes

Select the MPC905 when a single source must distribute clocks to multiple loads (up to 12) in a PCI architecture. It is suitable for designs requiring independent control of the main clock group (BCLK0–4) and the block clock (BCLK5) for power saving. Ensure the external crystal meets the specified ESR (50–80Ω) and shunt capacitance (5–7pF) for reliable oscillation at 33.3333 MHz or 11.1111 MHz.

Clock Buffers, Drivers Part Context

The MPC905 was originally manufactured by Motorola Semiconductor Products Inc., which later became NXP Semiconductors. It serves as a specialized timing solution for legacy PCI systems. The device is distinct from general-purpose clock buffers due to its integrated oscillator interface and specific synchronization features tailored for bus standards.

Clock Buffers, Drivers Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Designers should consult current NXP product portfolios for modern replacements, ensuring compatibility with LVCMOS levels and pin configurations if direct replacement is required.

Clock Buffers, Drivers FAQ

How does the MPC905 handle output disabling?

Both enable inputs are synchronized internally to ensure output disabling occurs only when outputs are already LOW, preventing runt pulses. Enable1 pulls BCLK0–BCLK4 low, while Enable2 pulls BCLK5 low. The oscillator continues running during these states.

What are the transmission line driving capabilities?

Each output has an approximate impedance of 10 Ω and can drive either one parallel-terminated 50 Ω line or two series-terminated 50 Ω lines. Series termination allows for higher fanout without DC current draw.

What crystal specifications are required?

For fundamental mode (33.3333 MHz), use an AT-cut crystal with 5–7 pF shunt capacitance and 50–80 Ω ESR. For third overtone (11.1111 MHz), additional trap components (CTRAP, LTRAP) are required as shown in Figure 2.