MPC9600FA

Overview

The MPC9600FA is a low voltage 2.5 V or 3.3 V compatible, 1:21 PLL-based clock driver and fanout buffer manufactured by NXP USA Inc. (formerly Motorola). It features an integrated phase-locked loop capable of multiplying input frequencies by 2, 3, 4, or 6 to generate output frequencies up to 200 MHz. The device provides 21 LVCMOS outputs organized into three selectable banks (QA, QB, QC) with maximum output-to-output skew of 150 ps and cycle-to-cycle jitter of ±50 ps. It accepts LVPECL or LVCMOS reference clocks and operates within a temperature range of -40°C to +85°C in a 48-lead LQFP package.

Feature Summary

• Integrated PLL supporting frequency multiplication factors of 2, 3, 4, and 6
• 21 LVCMOS outputs distributed across three fully selectable banks (QA0-QA6, QB0-QB6, QC0-QC6)
• Maximum output-to-output skew of 150 ps and ±50 ps cycle-to-cycle jitter
• Supports both LVPECL differential and LVCMOS single-ended reference clock inputs

Applications

• Nested clock tree architectures requiring zero-delay buffering
• High-performance systems demanding precise synchronization with minimal skew
• Clock distribution networks utilizing parallel or series terminated transmission lines

Procurement Notes

Verify the specific suffix 'FA' corresponds to the 48-lead LQFP package variant when sourcing. Confirm that the component meets the required operating temperature range of -40°C to +85°C for the intended environment. Ensure power supply filtering on the VCCA pin is implemented according to datasheet recommendations to maintain PLL stability and minimize jitter.

Selection Notes

Select this component when a single source must drive multiple loads with tight skew requirements. The device supports input frequencies from 16.67 MHz to 50 MHz. Designers must ensure the VCO frequency remains between 200 MHz and 400 MHz for stable operation. Consider the separate VCC and VCCA power pins; a filter circuit on VCCA is recommended to isolate analog PLL noise from digital switching noise.

Part Context

The MPC9600 is part of the Motorola/NXP timing solutions family designed for low-voltage CMOS applications. It serves as a bridge between high-speed differential clock sources and LVCMOS logic loads. The device replaces older discrete PLL and buffer combinations by integrating the feedback path and output drivers into a single 48-pin package.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.

FAQ

How does the MPC9600 achieve zero-delay buffering?

It uses an external feedback path where the QFB output is connected to the FB_IN input. The internal PLL aligns the feedback clock edge with the reference clock input edge, virtually eliminating propagation delay.

What is the purpose of the VCCA pin?

VCCA supplies the analog PLL circuitry. Driving VCCA to GND bypasses the PLL for static testing. A power supply filter is recommended on this pin to reduce jitter caused by system noise.

Can the MPC9600 drive multiple transmission lines per output?

Yes. While each output can drive one parallel terminated line, it can drive up to two series terminated lines per output, effectively doubling the total fanout capability to 1:42.