MPC99J93FA

Overview

The MPC99J93FA is a PLL clock driver and Intelligent Dynamic Clock Switch (IDCS) manufactured by NXP USA Inc. It accepts two differential LVPECL input signals and generates five new differential LVPECL outputs. Two output pairs regenerate the input frequency and phase, while three pairs generate 2x phase-aligned outputs. The device operates on a 3.3V supply with an input reference frequency range of 50 MHz to 90 MHz and a VCO frequency range of 200 MHz to 360 MHz. It features LVCMOS control I/O and is housed in a 32-lead LQFP package.

Feature Summary

• Intelligent Dynamic Clock Switch (IDCS) for redundant clock tree designs
• Fully integrated PLL with 200–360 MHz VCO frequency range
• Five differential LVPECL outputs: two 1x and three 2x phase-aligned pairs
• LVCMOS control inputs and outputs

Applications

• Redundant clock tree designs
• Systems requiring dynamic clock switching with minimal phase disturbance
• High-speed digital systems utilizing LVPECL interfaces

Procurement Notes

Verify that the FA suffix corresponds to the standard 32-lead LQFP package as defined in the Freescale Semiconductor datasheet Rev 3. Confirm that the component source matches the original manufacturer specifications for the MPC99J93 series. Ensure compatibility with 3.3V operation and LVPECL signal levels required by the target application circuitry.

Selection Notes

Select this component when designing redundant clock architectures requiring automatic failover between two LVPECL sources. The device supports a maximum output frequency of 180 MHz on the 2x outputs. Ensure the system design accommodates the specified thermal resistance values and provides proper termination voltage (VTT = VCC - 2V) for the LVPECL outputs to maintain AC characteristics.

Part Context

The MPC99J93 is part of the Advanced Clock Drivers Devices family originally released by Freescale Semiconductor. The 'FA' suffix indicates the specific 32-lead LQFP packaging variant. This component is designed to eliminate typical phase bumps during clock failure events by continuously monitoring input signals and switching to a secondary clock source seamlessly.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.

FAQ

How does the Intelligent Dynamic Clock Switch (IDCS) handle a clock failure?

The IDCS continuously monitors both input CLK signals. Upon detecting a failure (CLK stuck HIGH or LOW for at least one period), it latches the INP_BAD flag and switches to the good secondary clock, performing phase/frequency alignment with minimal output phase disturbance.

What is the function of the Qb output pairs?

The Qb0:2 output pairs generate 2x, phase-aligned clock outputs derived from the selected input reference signal.

What are the absolute maximum ratings for the supply voltage?

The absolute maximum continuous rating for the VCC Supply Voltage is -0.3 V to 3.9 V.