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— IC芯片 | 连接器 | 传感器 | 被动器件 —
The NP0G3D200A is a composite transistor array from Panasonic Electronic Components, integrating one silicon PNP epitaxial planar transistor (Tr1) and one silicon NPN epitaxial planar transistor (Tr2) into a single SSSMini6-F1 package. Designed for digital circuits, it features an internal connection scheme with six leads: Base (Tr1), Base (Tr2), Emitter (Tr2), Collector (Tr2), Emitter (Tr1), and Collector (Tr1). The device supports a maximum collector current of 80 mA for both transistors and operates within a total power dissipation limit of 125 mW at 25°C. It complies with the RoHS Directive.
Verify component status before procurement as this part may be discontinued or under maintenance plans. Consult official manufacturer lifecycle documentation for availability confirmation. Ensure compliance with specific handling requirements such as damp-proof packing conditions and shelf life limits upon opening packages to prevent characteristic changes.
Select this component when a matched PNP/NPN pair is required for digital switching or logic level translation. Verify that the 80 mA collector current and 50 V breakdown voltage meet circuit demands. Confirm thermal management capabilities align with the 125 mW total power dissipation rating under expected ambient temperature conditions.
This component belongs to the category of discrete semiconductor products, specifically pre-biased transistor arrays. It utilizes the SSSMini6-F1 surface mount package. The internal structure combines distinct PNP and NPN epitaxial planar technologies to provide a unified solution for complementary signal processing tasks.
The datasheet identifies UNR31AT and UNR32AL as basic part numbers associated with this configuration. Verify pinout compatibility and electrical specifications against these references before substitution.