NS7520B-1-C36

Overview

The Digi NS7520B-1-C36 is a 32-bit system-on-a-chip ASIC based on the ARM7TDMI core, designed for intelligent networked devices. It integrates a 10/100 Mbps Ethernet MAC, two independent serial ports (UART/SPI), and a 13-channel DMA controller. The device operates at a maximum frequency of 36 MHz with a 1.5 V core voltage and 3.3 V I/O voltage. It features five chip selects supporting Flash, SDRAM, SRAM, and EEPROM without external glue logic. Packaged in a 177-pin LFBGA, it supports commercial temperature ranges.

Feature Summary

• ARM7TDMI 32-bit RISC processor core operating up to 36 MHz
• Integrated 10/100 BaseT Ethernet MAC with MII interface
• Two independent serial ports configurable as UART or SPI
• Five chip select configurations for external memory support

Applications

• Intelligent networked devices
• Internet appliances
• Embedded networking solutions using NET+Works platform

Procurement Notes

Verify the specific suffix 'C36' confirms the 36 MHz operating grade and commercial temperature range against official Digi documentation. Ensure design compatibility with the 177-pin LFBGA package dimensions and 1.5V/3.3V power requirements during sourcing.

Selection Notes

Select this component when a 36 MHz ARM7TDMI solution with integrated Ethernet and serial interfaces is required. Compare against C46 and C55 grades if higher clock speeds are needed. Verify that the 177-pin footprint and pinout align with the target PCB layout constraints.

Part Context

This part belongs to the NS7520 family within the NET+ARM architecture. Variants include NS7520B-1-C46 (46 MHz) and NS7520B-1-C55 (55 MHz). All share the same ARM7TDMI core and peripheral set but differ in maximum operating frequency determined by bootstrap configuration.

Replacement Considerations

Direct functional replacements within the same package and pinout are limited to other NS7520 grades (C46, C55) which may require frequency limitation. Cross-family migration requires significant hardware redesign due to differing pinouts and core architectures.