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The NSBC124XDXV6T1G is a dual NPN Bias Resistor Transistor (BRT) from onsemi, integrating two NPN transistors with monolithic bias resistor networks in a single SOT-563 package. It replaces discrete components and external resistors to simplify circuit design. Key electrical parameters include a maximum collector-emitter voltage (VCEO) of 50 Vdc and a continuous collector current (IC) of 100 mAdc. The device features an input series base resistor (R1) of 22 kΩ and a base-emitter resistor (R2) of 47 kΩ. Thermal characteristics specify a total device dissipation of 500 mW at 25°C when both junctions are heated.
Verify the specific ordering suffix to confirm the package type and manufacturing compliance. The 'G' suffix indicates Pb-Free status. Confirm that the required variant meets AEC-Q101 qualification if the application demands automotive-grade reliability and PPAP capability. Ensure the selected part matches the intended pinout configuration for the target PCB footprint.
Select this component when a dual NPN configuration with integrated biasing is required. Verify that the 50 V collector-emitter voltage rating and 100 mA continuous current limit meet the circuit's operational demands. Consider the SOT-563 package dimensions for spatial constraints. For automotive applications requiring specific quality controls, choose the NSV prefix variant which supports PPAP documentation.
This device belongs to the DTC124XD series of dual NPN Bias Resistor Transistors. It shares functional similarities with other BRT families but is distinct in its specific resistor values and dual NPN topology. The product line aims to consolidate multiple discrete semiconductor components into a single surface-mount device to enhance assembly efficiency and circuit reliability.
Direct substitutes include MUN5234DW1T1G for SOT-363 packaging. Cross-package replacements require verifying identical electrical characteristics and pin configurations. Ensure any alternative maintains the same R1 and R2 resistance values to preserve the original circuit biasing conditions.