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NXU0204PW-Q100J is listed in the Translators, Level Shifters range at ChipApex. The manufacturer field lists Nexperia USA Inc.. Its product description is NXU0204PW-Q100/SOT402/TSSOP14. Review the specifications below when checking this part for your BOM.
The NXU0204PW-Q100J is a 4-bit dual-supply voltage level translating buffer with Schmitt-trigger inputs and 3-state outputs. It features four data inputs (A1, A2, B3, B4) and four outputs (YB1, YB2, YA3, YA4). Both VCCA and VCCB operate between 0.9 V and 5.5 V. Data transmits unidirectionally from the A bus to the B bus on three channels and from the B bus to the A bus on one channel. The maximum data rate reaches 250 Mbps for translations between 1.8 V and 5 V.
Verify the component matches the specific TSSOP-14 package configuration designated by the PW suffix. Confirm that the Q100 designation indicates compliance with Automotive Electronics Council Grade 1 requirements. Ensure the ordering code includes the correct temperature range extension for -40 °C to +125 °C operation. Cross-reference the marking code NXU0204 against the physical device to validate authenticity.
Select this component when asymmetric bidirectional translation is required, specifically needing three channels flowing from domain A to B and one channel from B to A. Choose this part over symmetric alternatives like the NXU0104 if the application demands mixed-direction data flow within a single package. Verify that the output enable pin can be referenced to the appropriate domain using the VCC(MIN) circuitry.
This device belongs to the Nexperia NXU0x04 family of 4-bit dual-supply voltage level translators. It shares functional similarities with the NXU0104-Q100 and NXU0304-Q100 but differs in channel directionality. The PW suffix identifies the plastic thin shrink small outline package with 14 leads and a body width of 4.4 mm.
NXU0104PW-Q100J
No power supply sequencing is required. The IOFF circuitry prevents damaging backflow currents if one supply is disconnected or floating, and output glitches during transitions are prevented.
The Output Enable (OE) pin allows connection to either the VCCA or VCCB domain. When set LOW, it disables the outputs and enters a high-impedance OFF-state to isolate the buses.
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