PBLS4002V,115

Overview

The PBLS4002V,115 is a dual pre-biased bipolar junction transistor (BJT) array manufactured by NXP USA Inc. It integrates one NPN and one PNP transistor within a single SOT-666 surface-mount package. The device features a maximum collector-emitter voltage of 50 V and supports continuous collector currents up to 100 mA for the NPN section and 500 mA for the PNP section. Typical base input resistance is 22 kOhms with a resistor ratio of 1. Operating temperature ranges from -65°C to +150°C.

Feature Summary

• Dual configuration combining NPN and PNP transistors in a compact footprint
• Integrated base bias resistors simplify circuit design
• High thermal stability supporting extended operating temperatures

Applications

• Digital switching circuits
• Logic level translation interfaces
• Driver stages for low-power loads

Procurement Notes

Verify component authenticity through authorized channels as this part is scheduled for obsolescence. Confirm final availability status directly with the manufacturer or certified distributors before integration into production timelines. Ensure compliance with RoHS3 directives and check for any product change notifications affecting pinout or electrical characteristics.

Selection Notes

Select this component when space-constrained designs require complementary NPN/PNP switching capabilities. The integrated resistors reduce external component count compared to discrete solutions. Evaluate thermal performance requirements against the 300 mW power dissipation limit and ensure the 50 V voltage rating exceeds peak circuit voltages.

Part Context

This device belongs to Nexperia's BISS loadswitch and pre-biased transistor portfolio. It serves as a cost-effective alternative to discrete transistor pairs in digital logic applications. The SOT-666 package provides efficient thermal management for small-signal operations while maintaining compatibility with standard surface-mount assembly processes.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Consult official Nexperia replacement guides for equivalent pre-biased dual transistor arrays.