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The Nexperia PBLS4005D,115 is a dual transistor array housed in a TSOP6 (SOT457) surface-mount package. It integrates a PNP low VCEsat transistor and an NPN resistor-equipped transistor (RET). The PNP section supports a collector current of up to 1 A with a maximum collector-emitter voltage of -40 V. The NPN RET provides an output current capability of 100 mA with a collector-emitter voltage rating of 50 V. Key electrical parameters include a typical bias resistor value of 47 kΩ for the NPN section and a transition frequency of 150 MHz for the PNP transistor.
Verify the specific ordering suffix against official Nexperia documentation to ensure correct packaging configuration. Confirm that the device meets all required environmental and qualification standards for the intended application before finalizing procurement decisions.
Select this component when a design requires both high-current switching and a pre-biased logic interface within limited board space. Ensure the operating conditions remain within the specified absolute maximum ratings for both the PNP and NPN sections to maintain device integrity.
This part belongs to the PBLS series of digital transistors manufactured by Nexperia. These devices are designed to simplify circuit design by integrating internal biasing resistors with bipolar junction transistors, offering a compact alternative to discrete component solutions.
Direct substitutes must match the TSOP6 (SOT457) package and contain identical PNP/NPN configurations with comparable voltage and current ratings. Verify pinout compatibility and thermal characteristics before implementation.