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The PBLS6023D,115 is a dual digital transistor in a SOT457 (SC-74) TSOP6 package. It integrates a PNP low VCEsat transistor and an NPN Resistor-Equipped Transistor (RET). The PNP section supports a collector-emitter voltage of -60 V and continuous current of -1.5 A, with a typical saturation resistance of 110 mΩ. The NPN RET features a 10 kΩ bias resistor and a ratio of 1. Qualified to AEC-Q101 standards, it operates within a junction temperature range of -55 °C to +150 °C.
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Select this component when a compact solution is required for high-side or load switching applications. The integrated NPN RET simplifies drive circuitry by providing built-in biasing, while the PNP transistor offers low saturation resistance for efficient power handling. Ensure the design accounts for the thermal characteristics specified for the target PCB footprint.
This device belongs to Nexperia's portfolio of digital transistors designed to replace discrete resistor-transistor networks. The PBLS6023D specifically targets applications requiring mixed polarity switching capabilities within a minimal surface-mount footprint, streamlining board layout for portable and automotive electronics.
Check pinout compatibility and electrical ratings against existing designs. Verify if alternative packages like SC-74 variants meet spatial constraints. Confirm that the replacement maintains the required AEC-Q101 qualification if used in automotive contexts.