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The PEMD17,115 is a dual NPN/PNP resistor-equipped transistor array housed in a SOT666 plastic surface-mounted package with six leads. It integrates an NPN transistor (TR1) and a PNP transistor (TR2), each featuring built-in bias resistors R1 and R2. The device supports a collector-emitter voltage of 50 V and a DC output current of 100 mA per transistor. Nominal bias resistor values are 47 kΩ for R1 and 22 kΩ for R2, yielding a ratio of 0.47. Total power dissipation is rated at 300 mW at 25 °C ambient temperature.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm packaging details. The -115 suffix corresponds to the SOT666 package variant supplied in tape and reel format. Confirm compliance requirements such as RoHS and REACH status directly from the latest datasheet revision before procurement.
Select the PEMD17 when a compact solution combining both NPN and PNP switching elements is required. Ensure the application operates within the 50 V collector-emitter voltage limit and 100 mA DC output current constraints. Verify that the integrated bias resistor values align with the target logic levels and drive requirements.
The PEMD17 belongs to the family of resistor-equipped transistors designed for high-density circuit designs. It serves as a complement to the PUMD17, which utilizes the SC-88 (SOT363) package. Both devices share identical electrical characteristics but differ in physical footprint and pin configuration to suit different board space constraints.
The PUMD17 offers equivalent electrical performance in the SOT363 package. Direct substitution requires verifying pin compatibility and ensuring the PCB footprint accommodates the alternative package dimensions.