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The PEMD18,115 is a dual digital transistor from Nexperia featuring one NPN and one PNP pre-biased element within a SOT-666 surface-mount package. It provides a maximum collector-emitter voltage (VCEO) of 50 V and a continuous collector current (IC) of 100 mA. The device incorporates typical input resistors of 4.7 kOhms with a resistor ratio of 0.47. Operating temperatures range from -65 °C to +150 °C, ensuring reliability across diverse industrial environments.
Verify the NRND status before initiating new designs, as this indicates the component is not recommended for future use. Confirm the specific suffix 115 matches the required reel packaging specifications. Ensure compliance with RoHS directives and check for any regional restrictions regarding precious metal content or Proposition 65 substances during final procurement validation.
Select this part when a matched NPN/PNP pair is required for push-pull or differential configurations. The integrated bias network eliminates the need for discrete base resistors, reducing component count. Verify that the 100 mA current rating and 50 V voltage limits align with the target application's electrical requirements.
This component belongs to the Nexperia PEMD series of digital transistors, designed for efficient signal switching. It shares the SOT-666 footprint with other variants like PEMH18 and PEMD2, allowing for potential pin-compatible design strategies within the same product family while offering distinct internal resistance configurations.
Publicly confirmed substitute part numbers are not available in the provided documentation. Designers should consult official Nexperia resources for cross-reference data or evaluate alternative digital transistors with matching SOT-666 packages and similar electrical characteristics.