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The PEMD19,115 is a dual pre-biased NPN/PNP digital transistor manufactured by Nexperia. It integrates two transistors with built-in bias resistors into a single SOT363 (SC-88) surface-mount package. The device features a maximum collector-emitter voltage of 50 V and a continuous collector current of 100 mA. Typical input resistance is 10 kΩ with a resistor ratio of 0.21. Operating temperature ranges from -65°C to +150°C. This component is designed for space-saving applications requiring logic-level switching or interface buffering.
Verify the specific suffix against official Nexperia documentation to confirm tape-and-reel packaging details. Ensure compliance with RoHS and REACH regulations as stated in the manufacturer's environmental declarations. Cross-reference the 12NC code for accurate ordering information.
Select this component when space constraints require integrated NPN/PNP pairs with fixed biasing. Verify that the 10 kΩ typical input resistance aligns with the driving source capabilities. Confirm that the 50 V voltage rating exceeds the maximum circuit operating voltage under all conditions.
This part belongs to the PEMD series of dual pre-biased transistors. It serves as a complement to the PUMD series, which typically offers different resistor ratios or configurations. Both series utilize the SOT363 package to provide compact solutions for digital switching tasks in modern electronic designs.
Check for direct pin-compatible alternatives within the Nexperia PEMD family. Verify if the PUMD series variants offer suitable electrical characteristics if the specific NPN/PNP configuration allows. Ensure any substitute maintains the same SOT363 package dimensions.