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The PEMD2,115 is a dual pre-biased transistor array manufactured by Nexperia USA Inc., housed in an SOT-666 surface-mount package. It integrates one NPN and one PNP bipolar junction transistor (BJT) with built-in bias resistors. The device supports a maximum collector-emitter voltage of 50 V and a continuous collector current of 100 mA. Key electrical parameters include a DC current gain (hFE) minimum of 60 at IC = 5 mA and VCE = 5 V, and a maximum collector-emitter saturation voltage of 150 mV at IB = 500 µA and IC = 10 mA. Power dissipation is rated at 300 mW.
Verify the specific ordering suffix and tape/reel specifications when sourcing. Confirm RoHS compliance and REACH status against current regulatory requirements. Check for end-of-life or not recommended for new design (NRND) status before finalizing procurement plans.
Select this component for designs requiring complementary NPN/PNP switching with integrated base resistors. Ensure the required hFE and saturation voltage meet the load drive specifications. Verify that the SOT-666 footprint matches the PCB layout constraints.
This part belongs to Nexperia's family of Resistor-Equipped Transistors (RET). These devices are designed to replace multiple discrete components, offering a space-saving solution for digital logic interfaces and signal conditioning tasks in consumer and automotive electronics.
Check for direct pin-compatible alternatives within the same RET family. Verify that substitute parts match the 50 V voltage rating and 100 mA current capability. Ensure equivalent saturation voltages and thermal performance for reliable operation.