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The Nexperia PEMH24,115 is a dual NPN Resistor-Equipped Transistor (RET) housed in a SOT666 plastic surface-mounted package. It integrates two NPN transistors with built-in bias resistors, where the typical input resistance R1 is 100 kΩ and the resistor ratio R2/R1 is 1. The device supports a maximum collector-emitter voltage of 50 V and a DC output current of 20 mA per transistor. Total power dissipation is rated at 300 mW for the device and 200 mW per transistor at 25 °C ambient temperature. The junction temperature limit is 150 °C, and it utilizes a 6-lead configuration.
Verify the specific ordering code suffix to confirm packaging details such as tape width and reel quantity. Confirm the product status via official Nexperia channels before finalizing procurement plans, as availability may change. Ensure compliance with relevant environmental directives during integration.
Select this component when space constraints require integrated biasing solutions. The SOT666 package offers a small footprint suitable for dense PCB layouts. Verify that the 20 mA DC output current meets the load requirements and that the 100 kΩ input resistance aligns with the driving source impedance.
The PEMH24 belongs to the NPN/NPN Resistor-Equipped Transistor family from Nexperia. It shares functional similarities with the PUMH24 but differs in package type, utilizing the SOT666 format instead of the SOT363. This series is designed to replace discrete transistor and resistor combinations in digital logic circuits.
Public confirmed substitute part numbers include PUMH24, which uses the SOT363 package. Designers must account for pinout differences and thermal characteristics when substituting between package types.
The typical value for the input bias resistor R1 is 100 kΩ.
The maximum collector-emitter voltage (VCEO) is 50 V.
The SOT666 package contains 6 leads.