PI6C20800SIVE

Overview

The PI6C20800SIVE is a PCI Express high-speed, low-noise differential clock buffer manufactured by Diodes Incorporated. It provides an 1:8 distribution ratio with eight pairs of differential HCSL outputs. The device supports both PLL and fanout operations, featuring a phase jitter filter for PCIe applications. It operates on a single 3.3V supply (3.135V to 3.465V) within the industrial temperature range of -40°C to +85°C. Key electrical parameters include a maximum input frequency of 400 MHz in bypass mode, output skew less than 50 ps, and cycle-to-cycle jitter under 70 ps. The component is housed in a 48-pin SSOP package.

Feature Summary

• PCIe Phase Jitter Filter: Designed as a companion to the PI6C410BS generator for Intel server chipsets.
• Differential Output: Distributes one SRC input to eight differential clock pairs with low skew (<50ps).
• Flexible Operation: Supports PLL or Fanout modes with programmable PLL bandwidth via hardware pins or SMBus.
• Control Interface: Includes SMBus control for output enable, tristate, and power management.

Applications

• PCI Express clock distribution for server chipsets.
• High-speed data transmission systems requiring low-noise clocking.
• Industrial temperature environment timing circuits.

Procurement Notes

Verify the specific suffix 'VE' corresponds to the 48-pin SSOP package and Industrial temperature grade (-40°C to +85°C). Confirm that the manufacturer designation has transitioned from Pericom to Diodes Incorporated. Check current availability status as legacy components may have limited stock or end-of-life implications.

Selection Notes

Select this part when an 8-output differential HCSL buffer with integrated jitter filtering is required for PCIe Gen I/II designs. Ensure the design accommodates the 3.3V supply voltage and utilizes the SMBus interface if dynamic output control is needed. Compare against the commercial grade version (PI6C20800SIVE vs SIVE) if operating temperatures exceed 70°C.

Part Context

This component belongs to the PI6C20800S series of PCIe clock buffers. It is functionally similar to the PI6C20800VE but differs in packaging (SSOP vs Tube) and temperature rating (Industrial vs Commercial). The 'I' suffix denotes the industrial temperature range, while 'V' indicates the SSOP package type.

Replacement Considerations

Direct pin-compatible replacements within the same family include the PI6C20800SIAEX (TSSOP package, Industrial temp) or PI6C20800SAE (TSSOP, Commercial). Verify package dimensions and thermal characteristics when substituting between SSOP and TSSOP variants.

FAQ

How is the input frequency divided?

The input SRC clock can be divided by 2 when the SRC_DIV# pin is held LOW.

What controls the output state during power down?

When PWRDWN# is asserted LOW, the outputs are controlled by the SMBus or hardware settings; specifically, they can be set to drive or tristate based on Control Register bits.

What is the maximum input frequency in bypass mode?

In Bypass Mode, the maximum input frequency is 400 MHz.