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The PI6C557-03AQE is a PCIe 2.0 compliant spread spectrum clock generator manufactured by Diodes Incorporated. It features a Phase-Locked Loop (PLL) and crystal driver to produce two differential HCSL outputs from a 25MHz input. The device supports output frequencies of 25, 100, 125, and 200MHz with selectable spread spectrum modulation of -0.5%, -0.75%, or no spread. It operates on a 3.3V ±10% supply voltage within an industrial temperature range of -40°C to +85°C. The component is housed in a 16-pin QSOP package.
Verify the ordering suffix 'Q' corresponds to the 16-pin QSOP package configuration. Confirm that the 'E' suffix indicates tape and reel packaging if required for automated assembly. Ensure the specific revision level matches the design requirements, as datasheet revisions may update electrical characteristics or mechanical dimensions.
Select this component when a 25MHz reference is available and differential HCSL outputs are required for PCIe 2.0 interfaces. Use the S1/S0 pins to set the desired frequency among 25, 100, 125, or 200MHz. Utilize the SS1/SS0 pins to enable spread spectrum if EMI mitigation is necessary. Ensure the PCB layout accommodates the 16-QSOP footprint and provides adequate decoupling capacitors near VDD pins.
The PI6C557-03A series includes variants such as PI6C557-03ALE (TSSOP) and PI6C557-03BQE (QSOP). The PI6C557-03AQE specifically denotes the QSOP package variant. Other family members may support different output types or PCIe generations, but this part is explicitly qualified for PCIe 2.0 standards.
PI6C557-03ALE serves as a functional equivalent in a TSSOP-16 package. For QSOP-16 replacements, verify pinout compatibility with other PCIe 2.0 clock generators from Diodes Incorporated or alternative manufacturers offering identical HCSL output specifications and 25MHz input requirements.
The output frequency is determined by the logic levels on pins S1 and S0. A combination of 00 selects 25MHz, 01 selects 100MHz, 10 selects 125MHz, and 11 selects 200MHz.
The device exhibits a typical RMS phase jitter of 2.1ps and a cycle-to-cycle jitter of 35ps at 100MHz output, complying with PCIe 2.0 test methods.
Yes, spread spectrum can be disabled by setting both SS1 and SS0 pins to a high logic level, resulting in no frequency modulation.