PI6CB332020AZXBEX-13R

Overview

The PI6CB332020AZXBEX-13R is a low-power PCIe 5.0/6.0 and PCIe 7.0 compatible clock buffer manufactured by Diodes Incorporated. It fans out one differential HCSL input into 20 low-power differential outputs, supporting frequencies up to 400MHz with on-chip termination for 85Ω output impedance. The device operates on a 3.3V supply voltage (2.97V to 3.63V) and features individual output enables, Power Down Tolerant (PDT) support, and automatic output clock parking upon loss of input clock. It is housed in an 80-VFQFN package (6mm × 6mm) and functions within an industrial temperature range of –40°C to 105°C.

Feature Summary

• Provides 20 low-power HCSL outputs with on-chip termination for 85Ω and 100Ω output impedance.
• Features individual OE pins for each output to facilitate easier power management.
• Supports SMBus interface with up to 9 selectable addresses and Side-Band Interface (SBI) for output control.
• Delivers ultra-low additive phase jitter: typical 3fs RMS for PCIe 6.0 and 5fs RMS for PCIe 5.0.

Applications

• PCIe 5.0 and PCIe 6.0 compliant system designs
• PCIe 7.0 application development
• High-performance server and storage backplanes

Procurement Notes

Verify the specific suffix 'ZXBEX-13R' against the manufacturer's official documentation to confirm packaging details and tape-and-reel quantities. Ensure that the ordering information matches the exact component designation required for the design, as suffixes may indicate variations in shipping or handling specifications.

Selection Notes

Select this component when a high-fanout clock distribution solution is required for PCIe 5.0/6.0/7.0 architectures. It is suitable for designs needing precise timing with minimal jitter addition and flexible output enablement via hardware pins or SMBus/SBI commands. Ensure the PCB layout accommodates the 80-pin QFN package and provides adequate thermal dissipation for the exposed pad.

Part Context

This part belongs to the PI6CB332020A series from Diodes Incorporated, specifically designed for next-generation PCI Express standards. It serves as a critical timing element in complex digital systems where signal integrity and low power consumption are paramount. The device integrates advanced features like automatic clock parking and flexible startup sequencing to enhance system reliability.

Replacement Considerations

Direct replacements must match the 20-output configuration, 400MHz frequency limit, and 80-VFQFN package. Verify compatibility with existing SMBus addressing schemes and ensure that any substitute supports the same PCIe generation jitter requirements and voltage ranges.

FAQ

What is the maximum operating frequency of the PI6CB332020A?

The device supports output frequencies up to 400MHz.

How does the device handle input clock loss?

It features Automatic Output Clock Parking (ACP), which automatically parks the outputs to a low/low state upon detection of an input clock loss event.

Can the output slew rate be controlled individually?

Yes, the device allows individual control over the slew rate for each output pair via SMBus registers, enabling selection between high and low slew rates.