PI6CDBL402BLIE

Overview

The PI6CDBL402BLIE is a PCIe 3.0 compliant, low-power differential clock buffer designed as a companion to PCIe 3.0 clock generators. It distributes a differential SRC clock input to four differential pairs of outputs in either PLL or bypass mode. The device supports independent output power supplies ranging from 1.8V to 3.3V and operates on a 3.3V core supply. Key electrical parameters include a maximum bypass frequency of 400 MHz and a typical cycle-to-cycle jitter of 45 ps at 100 MHz. It features an SMBus interface for configuration and is housed in a 28-TSSOP package.

Feature Summary

• PCIe 3.0/2.0/1.0 compliant with phase jitter filtering capabilities
• Four differential output pairs supporting HCSL and LVDS formats
• Independent output power supply range of 1.8V to 3.3V
• SMBus interface for programmable control and status monitoring

Applications

• PCI Express (PCIe) 3.0 clock distribution systems
• High-speed data transmission equipment requiring low-noise clocks
• Server and storage infrastructure clocking solutions

Procurement Notes

Verify the ordering suffix 'E' confirms Pb-free and Green compliance. Confirm the package type matches the 28-TSSOP specification. Ensure the design supports the required voltage levels for VDDA and VDDO. Check for specific tape and reel requirements if applicable.

Selection Notes

Select this component when a low-power, multi-output buffer is needed for PCIe applications. Consider the 1.8V to 3.3V output supply flexibility for mixed-voltage systems. Evaluate the SMBus requirement for dynamic configuration against simpler hardware-controlled alternatives.

Part Context

This part belongs to the PI6CDBL402B series of low-power PCIe buffers. It is manufactured by Diodes Incorporated, formerly Pericom Semiconductor. The device is specifically engineered to meet the stringent jitter and power requirements of modern high-speed serial interfaces.

Replacement Considerations

Direct replacements within the same family include PI6CDBL402BLIEX (Tape & Reel variant). Verify pinout compatibility and electrical specifications before substituting with other clock buffer models.

FAQ

What are the supported output voltage ranges?

The device supports independent output power supplies (VDDO) ranging from 1.8V to 3.3V.

How is the PLL operation controlled?

PLL operation is selected via the PLL/BYPASS# pin or through the SMBus interface.

What is the maximum operating frequency in bypass mode?

The maximum operating frequency in bypass mode is 400 MHz.