PI6CEQ20200LIEX

Overview

The PI6CEQ20200LIEX is a PCIe Gen2/Gen3 zero-delay buffer manufactured by Diodes Incorporated, housed in a 20-TSSOP package. It features one HCSL differential input and two HCSL differential outputs with a 1:2 ratio. The device operates on a 3.135V to 3.465V supply within an industrial temperature range of -40°C to +85°C. Key electrical parameters include a maximum frequency of 110MHz, cycle-to-cycle jitter of 40ps typical, and output-to-output skew under 10ps. It integrates internal equalization for signal integrity improvement.

Feature Summary

• PCIe Gen2/Gen3 compliant zero-delay buffer with dual PLL bandwidth for spread-spectrum clocking tracking
• Proprietary internal equalization technique enhances signal integrity for long-distance clock paths
• Supports SMBus configuration via SCLK and SDATA pins for dynamic control
• Low power consumption with total supply current limited to 65mA under recommended operating conditions

Applications

• Servers
• Embedded computing systems
• Networking systems

Procurement Notes

Verify the ordering suffix 'E' confirms Pb-free and Green status, while 'X' indicates Tape & Reel packaging. Confirm the 'I' suffix matches the required -40°C to +85°C industrial temperature grade. Ensure the 20-TSSOP (0.173 inch width) package dimensions align with the PCB footprint requirements before finalizing procurement orders.

Selection Notes

Select this component when designing PCIe Gen2 or Gen3 interfaces requiring low skew and high signal integrity over long traces. The dual PLL bandwidth selection allows optimization for specific spread-spectrum clocking frequencies. Ensure the design accommodates the 3.3V supply voltage and provides adequate thermal dissipation for the TSSOP-20 package within the specified ambient temperature limits.

Part Context

This part belongs to the PI6CEQ series of PCIe clock buffers produced by Diodes Incorporated (formerly Pericom). It serves as a specialized timing solution for high-speed serial interfaces, replacing standard oscillators or buffers that lack integrated equalization and zero-delay buffering capabilities required for modern PCIe compliance.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Verify pinout compatibility and electrical specifications against alternative PCIe clock generators if sourcing from different manufacturers.

FAQ

What is the function of the PLL_BW_SEL pin?

The PLL_BW_SEL pin selects the PLL loop bandwidth. A logic high sets a high bandwidth (1.3MHz to 3MHz), while a logic low sets a low bandwidth (0.25MHz to 1MHz).

How does the device handle output enablement?

Outputs are controlled by OE_0# and OE_1# pins. A logic low enables the respective outputs, while a logic high tri-states them. These pins have internal pull-down resistors.

What is the maximum propagation delay in bypass mode?

In bypass mode, where the PLL is disabled, the maximum propagation delay is 4.0 ns.