PI6LC48H02-01LIE

Overview

The PI6LC48H02-01LIE is a clock generator compliant with PCI Express 3.0/2.0/1.0 and Ethernet standards, designed for servers, networking, and embedded systems. It accepts a 25MHz crystal or clock input and generates two differential HCSL outputs at selectable frequencies of 25MHz, 100MHz, 125MHz, or 200MHz via S0/S1 pins. The device operates on a single +3.3V supply (±10%) within an industrial temperature range (-40°C to +85°C). Key electrical parameters include a typical cycle-to-cycle jitter of 35ps and RMS phase jitter of 0.32ps at 100MHz (12kHz–20MHz bandwidth). It features power-down mode and is available in a lead-free 16-pin TSSOP package.

Feature Summary

• PCIe 3.0/2.0/1.0 compliant with ultra-low phase jitter (0.45ps RMS High Freq Typ.)
• Generates 25MHz, 100MHz, 125MHz, or 200MHz from a 25MHz input
• Two differential HCSL outputs with LVDS compatibility
• Industrial temperature range (-40°C to +85°C) and power-down mode

Applications

• PCI Express interface clock generation
• Server and networking system timing
• Embedded systems requiring low-jitter reference clocks

Procurement Notes

Verify the ordering suffix 'LIE' corresponds to the Pb-free, Green, 16-pin TSSOP package configuration. Confirm that the 'X' suffix is required if tape and reel packaging is needed instead of the standard tube. Ensure the design supports the specific 3.3V supply voltage requirements and thermal characteristics defined in the datasheet.

Selection Notes

Select this component when PCIe 3.0/2.0/1.0 compliance is mandatory. Use the S0 and S1 pins to configure the desired output frequency among 25MHz, 100MHz, 125MHz, and 200MHz. Ensure the application can accommodate the external termination resistors (RS=33Ω, RT=49.9Ω) and decoupling capacitors specified for HCSL output integrity.

Part Context

This part belongs to the PI6LC48 family of HiFlex clock generators. The 'H02-01' designation specifically indicates the dual HCSL output variant optimized for PCIe applications. It shares the core PLL architecture with other variants in the series but differs in output driver type and pinout configuration.

Replacement Considerations

Public confirmed substitute part numbers are not provided in the source material.