PI6LC48P0201AZHIEX

Overview

The PI6LC48P0201AZHIEX is a 2-output LVPECL synthesizer optimized for Ethernet reference clock generation, belonging to the HiFlex family. It utilizes a 25MHz crystal or single-ended LVCMOS/LVTTL input to generate frequencies of 62.5MHz, 125MHz, and 156.25MHz via two frequency select pins. The device features ultra-low phase jitter, with typical RMS values of 0.3ps at 156.25MHz (12kHz–20MHz). It supports full 3.3V or 2.5V supply modes and operates within an industrial temperature range (-40°C to +85°C).

Feature Summary

• Two differential LVPECL output pairs with selectable crystal or CMOS/TTL input.
• Generates standard Ethernet frequencies: 62.5MHz, 125MHz, and 156.25MHz.
• Ultra-low phase jitter: 0.3ps typical RMS (12kHz–20MHz) at 156.25MHz.
• Supports dual voltage supplies: 3.3V ±10% or 2.5V ±5%.

Applications

• Networking systems requiring Ethernet reference clocks.
• High-performance clock solutions for network interface cards.
• Systems utilizing Pericom HiFlex family timing architectures.

Procurement Notes

Verify the ordering suffix 'EX' confirms tape and reel packaging for this specific part number. Confirm the 'ZH' suffix indicates the 20-pin TQFN package type. Ensure the component meets Pb-free and Green environmental standards as specified in the manufacturer's ordering information.

Selection Notes

Select this component when low phase jitter is critical for Ethernet interfaces. Choose between crystal oscillator or single-ended input based on system design. Ensure power supply rails match the required 3.3V or 2.5V operation mode. Verify thermal requirements against the junction-to-ambient resistance of 19.80°C/W.

Part Context

This part is manufactured by Diodes Incorporated under the Pericom brand. It is part of the HiFlex family of high-performance clock solutions. The device is designed to replace legacy networking clock generators while providing improved jitter performance and flexible input options.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Consult manufacturer resources for cross-reference data if replacement is necessary.

FAQ

How is the output frequency determined?

The output frequency is selected using two frequency select pins (N_SEL0 and N_SEL1) when using a 25MHz crystal, supporting outputs of 62.5MHz, 125MHz, or 156.25MHz.

What is the maximum RMS phase jitter specification?

The maximum RMS phase jitter is 0.5ps at 156.25MHz (12kHz–20MHz), 0.55ps at 125MHz, and 0.7ps at 62.5MHz.

Can unused inputs be left floating?

Yes, unused crystal inputs (XTAL_IN/OUT) and Ref_IN can be left floating, though tying them to ground via a 1kΩ resistor provides additional protection.