PI6LC48P25104LE

Overview

The PI6LC48P25104LE is a single-output LVPECL clock synthesizer from the HiFlex family, designed for Ethernet reference clock generation. It operates on 3.3V or 2.5V supplies and accepts a 25MHz crystal input to produce 156.25MHz or 187.5MHz outputs via Freq_SEL configuration. The device utilizes proprietary low phase noise PLL technology, achieving typical RMS phase jitter of 0.3ps at 156.25MHz (12kHz-20MHz). Packaged in an 8-pin TSSOP, it supports commercial temperature ranges.

Feature Summary

• Single differential LVPECL output with frequency range 145MHz to 187.5MHz
• Ultra-low RMS phase jitter: 0.3ps typical at 156.25MHz (12kHz-20MHz)
• Dual supply mode support: 3.3V or 2.5V operation
• Freq_SEL pin allows selection between 156.25MHz and 187.5MHz using a 25MHz crystal

Applications

• Networking systems
• Servers and storage systems
• SATA/SAS interfaces
• Ethernet interface applications

Procurement Notes

Verify component authenticity through authorized Diodes Incorporated channels. Confirm package marking matches the ordering code PI6LC48P25104LE for lead-free green 8-pin TSSOP. Check datasheet revisions for any updates regarding thermal characteristics or packaging changes before finalizing procurement specifications.

Selection Notes

Select this component when a single-ended LVPECL clock source is required for high-speed networking or storage interfaces. Ensure the design accommodates separate VDD and VDDA power pins with appropriate filtering (0.1μF bypass capacitors) to maintain specified jitter performance. Verify that the system environment falls within the commercial operating temperature range (-40°C to +85°C).

Part Context

This part belongs to the Pericom HiFlex family of clock solutions, now manufactured by Diodes Incorporated following their acquisition. The PI6LC48P25104 specifically targets Ethernet reference clock generation, offering a compact alternative to discrete oscillator solutions while providing programmable frequency multiplication via external crystal inputs.

Replacement Considerations

No direct public substitute part numbers are documented in the provided datasheet. Designers requiring replacement should evaluate other HiFlex series clock generators with compatible LVPECL outputs and similar frequency ranges, ensuring pinout compatibility or implementing necessary PCB redesigns.

FAQ

How is the output frequency selected?

The output frequency is determined by the Freq_SEL pin state. When Freq_SEL is LOW, the output is multiplied by 6.25 (yielding 156.25MHz with a 25MHz crystal). When HIGH, it is multiplied by 7.5 (yielding 187.5MHz).

What are the power supply requirements?

The device supports full 3.3V or 2.5V supply modes. VDD (core) and VDDA (analog) must be individually connected to the power plane with 0.1μF bypass capacitors. For optimal jitter performance, VDDA requires an additional 10Ω resistor and 10μF capacitor.

What is the typical phase jitter performance?

Using a 25MHz crystal, the typical RMS phase jitter is 0.3ps at 156.25MHz and 0.33ps at 187.5MHz, measured over the 12kHz to 20MHz offset frequency range.