PI6PCIEB24ZDEX

Overview

The PI6PCIEB24ZDEX is a 1:4 PCI Express 2.0 compliant high-speed differential clock driver manufactured by Diodes Incorporated. It distributes an input differential PCIe clock to four differential pairs of outputs using a zero-delay PLL. The device operates at 3.3V with a maximum frequency of 100 MHz in PLL mode. Key electrical parameters include propagation delay within ±250ps, output-to-output skew under 50ps, cycle-to-cycle jitter below 50ps, and additive RMS phase jitter less than 1ps. It utilizes a 20-pin TQFN package (ZD20) measuring 4.0mm x 4.0mm.

Feature Summary

• PCIe 2.0 compliant 1:4 differential clock buffer with zero-delay PLL
• Low jitter performance: <50ps cycle-to-cycle and <1ps additive RMS phase jitter
• Low skew (<50ps) and propagation delay (±250ps)
• Configurable output current via external IREF resistor

Applications

• PCI Express 2.0 system clock distribution
• High-speed data acquisition systems requiring low-jitter clocks
• Telecommunications equipment clocking

Procurement Notes

Verify the ZDEX suffix indicates Tape/Reel packaging as per datasheet ordering information. Confirm RoHS compliance and Green status for environmental requirements. Ensure the application supports the 3.3V supply voltage range of 3.135V to 3.465V. Check thermal management needs for the TQFN package.

Selection Notes

Select this component when a single-ended or differential source must drive four independent PCIe 2.0 loads with minimal skew. The internal PLL allows operation up to 100 MHz. Designers must provide an external resistor on the IREF pin to set the output current accurately. Bypass mode is available via the PLL/BYPASS# pin for testing.

Part Context

This part belongs to the Pericom PI6PCIEB24 family of PCIe clock drivers. The 'ZD' suffix denotes the 20-pin TQFN package, while 'E' signifies Pb-free and Green manufacturing. The 'X' suffix specifically indicates the unit is supplied in a tape and reel format for automated assembly.

Replacement Considerations

Direct replacement requires matching the 1:4 differential output topology and TQFN-20 package. Verify that alternative devices support the same 3.3V operation and PCIe 2.0 jitter specifications.

FAQ

How is the output current configured?

The differential output current is set by connecting an external resistor to the IREF pin. The nominal test load configuration typically uses a 475Ω resistor.

What is the function of the PLL/BYPASS# pin?

When driven HIGH, the internal PLL is enabled for normal operation. When driven LOW, the PLL is bypassed, allowing direct signal transmission with a delay of 2.5ns to 6.5ns.

What is the maximum operating frequency?

The device supports a maximum frequency of 100 MHz when operating in PLL mode.