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— IC芯片 | 连接器 | 传感器 | 被动器件 —
The PI6ULS5V9627AQE is a 4-channel level translating Fast-Mode Plus I2C-bus/SMBus repeater manufactured by Diodes Incorporated. It provides bidirectional buffering for serial data (SDA) and clock (SCL) lines, isolating capacitance to support up to 540pF on either side at 1 MHz or 4000 pF at lower speeds. The device translates voltage levels from Port A (0.6V to 5.5V) to Port B (2.2V to 5.5V). It operates with an active HIGH enable input referenced to VCC(B), supports arbitration and clock stretching, and features powered-off high-impedance pins. ESD protection exceeds 8000V HBM.
Verify the ordering suffix 'QEX' corresponds to the QSOP-16L package and tape/reel shipping format. Confirm the 'E' suffix indicates lead-free and green material compliance. Ensure the component matches the specific datasheet revision DS40171 Rev 1-2 for accurate electrical characteristics.
Select this component when system design requires bridging a 0.6V logic domain with a 2.2V to 5.5V domain while maintaining I2C protocol integrity. It is suitable for applications needing isolation of bus capacitance exceeding standard limits. Verify that the enable pin control logic aligns with the VCC(B) reference requirements.
This part belongs to the PI6ULS5V9627A series of interface ICs designed for I2C and SMBus applications. It serves as a signal buffer and repeater to expand bus capabilities. The 'QE' suffix denotes the specific QSOP-16L package variant within the broader product family.
Public confirmed substitute part numbers are not available in the provided documentation. Designers should consult official manufacturer resources for cross-reference information if alternative sourcing is required.
No, the device requires VCC(B) to be above 2.2V and VCC(A) above 0.6V for normal operation. However, the I/O pins remain high-impedance when unpowered.
The maximum propagation delay is 173 ns for HIGH-to-LOW transitions from Port A to Port B, and 152 ns for LOW-to-HIGH transitions from Port B to Port A.
The PI6ULS5V9627A supports arbitration and clock stretching across the repeater, allowing multiple masters to function correctly on the extended bus segments.