PMBT3904YS,115

Overview

The PMBT3904YS,115 is a dual NPN general-purpose transistor manufactured by Nexperia. It integrates two transistors in a TSSOP6 (SOT363-3) surface-mount package. Key electrical parameters include a collector-emitter voltage of 40 V and a continuous collector current of 200 mA per transistor. The DC current gain ranges from 100 to 300 at 10 mA. Total power dissipation is limited to 350 mW for the device and 230 mW per transistor. Transition frequency reaches 300 MHz, with saturation voltages of 120 mV at 50 mA.

Feature Summary

• Integrates two NPN transistors into a single compact SMD plastic package
• Designed for board-space reduction in dense circuit layouts
• Suitable for general-purpose switching and amplification tasks

Applications

• General-purpose switching circuits
• Amplification applications

Procurement Notes

Verify the specific ordering suffix against the manufacturer's official documentation to confirm packaging details such as reel or cut tape specifications. Ensure that the component version matches the required production data sheet revision. Confirm RoHS compliance status through the supplier's declaration before finalizing procurement orders.

Selection Notes

Select this component when space constraints require integrating two NPN switching functions into one footprint. Verify that the 40 V collector-emitter voltage rating meets the circuit requirements. Check thermal resistance values if operating near the maximum power dissipation limits in free air or on FR4 PCBs.

Part Context

This part belongs to the PMBT3904 series of small-signal NPN transistors. It differs from single-transistor variants like the PMBT3904 by providing two devices in one package. The SOT363-3 package offers a smaller footprint compared to traditional dual transistor packages, facilitating higher density designs.

Replacement Considerations

Direct replacements must match the dual NPN configuration and SOT363-3 package. Verify pinout compatibility, specifically the emitter-base-collector arrangement for both transistors within the six-lead outline.