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The PQMD12 is an NPN/PNP double Resistor-Equipped Transistor (RET) housed in a leadless DFN1010B-6 (SOT1216) package. It integrates two transistors with built-in bias resistors, where R1 is typically 47 kΩ and the R2/R1 ratio is 1. The device supports a maximum collector-emitter voltage (VCEO) of 50 V and an output current (IO) of 100 mA per transistor. Total power dissipation reaches 350 mW at 25 °C ambient temperature. The junction temperature limit is 150 °C, and it operates within an ambient range of -55 °C to +150 °C.
Verify the specific ordering code against the manufacturer's official documentation to ensure correct package variant and marking configuration. Confirm that the DFN1010B-6 footprint matches the target PCB layout requirements. Check for any recent revision history updates regarding marking codes or thermal characteristics before finalizing procurement specifications.
Select this component when a compact dual-transistor solution with integrated biasing is required. Ensure the 100 mA current rating and 50 V voltage limits accommodate the circuit load. Consider the 350 mW total power dissipation capability and verify thermal management on the FR4 PCB meets the derating curve requirements for the intended operating environment.
This part belongs to Nexperia's portfolio of resistor-equipped transistors designed to reduce component count and assembly costs. It utilizes the SOT1216 leadless ultra-thin small outline package, which is optimized for surface-mount technology. The product line targets applications requiring high integration density and simplified digital switching logic.
Direct replacements must match the DFN1010B-6 package, pinout configuration, and electrical ratings. Verify equivalent R1 resistance values and hFE gain ranges. Cross-reference with other Nexperia RET series parts sharing the SOT1216 footprint if pin compatibility is critical.
The typical value for the built-in base resistor R1 is 47 kΩ, with a range from 33 kΩ to 61 kΩ.
Yes, the product has been qualified in accordance with the AEC-Q101 standard for discrete semiconductors.
The maximum total power dissipation is 350 mW when the ambient temperature is 25 °C or lower.