PSD813F1A-12UI

Overview

The PSD813F1A-12UI is a Flash in-system programmable (ISP) peripheral for 8-bit MCUs, operating on a single 5 V ± 10% supply. It integrates 1 Mbit of primary Flash memory organized into eight uniform sectors and 256 Kbit of secondary EEPROM with four uniform sectors. The device includes 16 Kbit of SRAM and over 3,000 gates of programmable logic (PLD), supporting both DPLD and CPLD architectures. It features 27 reconfigurable I/O ports and an enhanced JTAG serial port for full-chip ISP. The component is housed in a 64-TQFP package.

Feature Summary

• Dual bank memories: 1 Mbit Primary Flash and 256 Kbit Secondary EEPROM with concurrent read/write/erase operations
• Over 3,000 gates of PLD architecture including 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
• Enhanced JTAG serial port enabling full-chip In-System Programmability without MCU participation
• 27 individually configurable I/O ports with support for open-drain outputs and latched address functions

Applications

• In-System Programming (ISP) via JTAG for field firmware updates
• In-Application Programming (IAP) allowing code execution from one memory while erasing/programming the other
• Expansion of microcontroller address space using the internal page register
• Programmable logic decoding for complex memory mapping in embedded designs

Procurement Notes

Verify that the specific ordering suffix corresponds to the required voltage level and package type. Confirm RoHS compliance status as indicated by the manufacturer's current documentation. Ensure compatibility with the target 8-bit MCU bus interface before procurement.

Selection Notes

Select this component when designing systems requiring simultaneous code execution and data storage updates. The dual-bank architecture supports concurrent operations, eliminating the need for external memory swapping during firmware updates. Verify that the 5 V supply requirement aligns with the system power rails.

Part Context

This device belongs to the PSD4000 series of Programmable Microcontroller Peripherals. It combines Flash memory, EEPROM, SRAM, and programmable logic into a single chip to simplify embedded system designs. The series is designed to provide flexibility for 8-bit MCU applications through integrated ISP capabilities.

Replacement Considerations

Check for pin-compatible alternatives within the same PSD family that may offer different memory capacities or voltage levels. Ensure any substitute maintains the JTAG interface and PLD gate count requirements for the existing design.

FAQ

Can the PSD813F1A be programmed while soldered to the circuit board?

Yes, the device features an enhanced JTAG serial port that allows full-chip In-System Programmability (ISP) while soldered to the board, without requiring MCU participation.

What is the endurance rating for the Flash memory?

The Flash memory has a high endurance rating of 100,000 erase/write cycles.

How does the device handle simultaneous read and write operations?

The dual-bank architecture allows concurrent operation, enabling the MCU to read from one memory bank while erasing and writing to the other.