PSD813F1A-90J

Overview

The PSD813F1A-90J is a Flash in-system programmable (ISP) peripheral for 8-bit MCUs, manufactured by STMicroelectronics. It integrates 1 Mbit of Primary Flash Memory and 256 Kbit of Secondary EEPROM, allowing concurrent read/write operations between the two arrays. The device includes 16 Kbit of SRAM and over 3,000 gates of programmable logic (DPLD and CPLD). It features 27 reconfigurable I/Os and supports a single 5 V supply voltage with standby current as low as 50 µA. The component is housed in a 52-pin PLCC package.

Feature Summary

• Dual bank memory architecture: 1 Mbit Primary Flash and 256 Kbit Secondary EEPROM with concurrent operation capability.
• Integrated programmable logic containing over 3,000 gates, including a Decode PLD (DPLD) and a Complex PLD (CPLD) with 16 Output Macrocells.
• Supports In-System Programming (ISP) via an IEEE 1149.1 compliant JTAG interface without MCU participation.
• Includes 16 Kbit SRAM and a built-in page register to expand the microcontroller address space by a factor of 256.

Applications

• In-Application Programming (IAP) for embedded firmware updates over communication channels such as CAN or Ethernet.
• Replacing complex discrete logic and memory components in 8-bit MCU-based designs.
• Automated manufacturing programming of blank devices soldered directly to circuit boards.

Procurement Notes

Verify that the design does not require new development, as this product is not recommended for new designs. Confirm compatibility with existing 8-bit MCU architectures and ensure the 52-PLCC package fits the target PCB footprint. Check for RoHS compliance status if required by specific regional regulations.

Selection Notes

Select this component when simultaneous code execution and data logging are required using separate Flash and EEPROM banks. Ensure the application utilizes an 8-bit MCU compatible with the multiplexed or non-multiplexed bus interfaces described in the datasheet. Verify that the 5 V supply voltage aligns with the system power requirements.

Part Context

This part belongs to the PSD813F1A family of Programmable Microcontroller Peripherals from STMicroelectronics. The 'J' suffix indicates the 52-pin Plastic Leaded Chip Carrier (PLCC) package variant. Other variants in the series include PQFP52 and TQFP64 packages, offering different form factors for similar functional capabilities.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Designers should consult STMicroelectronics for current alternative recommendations within the PSD family or general-purpose programmable peripherals.

FAQ

Can the PSD813F1A be programmed while installed on the board?

Yes, it supports In-System Programming (ISP) via a standard JTAG interface, allowing the Flash memory, EEPROM, and PLD to be programmed without removing the device from the circuit.

What is the endurance rating for the Flash memory?

The Primary Flash Memory has an endurance of 100,000 Erase/Write cycles, while the Secondary EEPROM supports 10,000 Erase/Write cycles.

How does the device handle simultaneous read and write operations?

The dual-bank architecture allows the MCU to execute code from one memory array (e.g., Flash) while simultaneously erasing and writing to the other array (e.g., EEPROM).