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— IC芯片 | 连接器 | 传感器 | 被动器件 —
The PT5161LC is a 16-lane PCI Express Gen-5 and Compute Express Link protocol-aware low-latency retimer. It supports data rates of 32 GT/s, 16 GT/s, 8 GT/s, 5 GT/s, and 2.5 GT/s with automatic link equalization. The device extends signal reach by over 36 dB at 32 GT/s using an 8.9 mm x 22.8 mm FC-CSP package. It features integrated AC-coupling capacitors, HCSL reference clock output, and flexible link bifurcation including 1x16, 2x8, and 4x4 configurations.
Verify the exact ordering suffix against official Astera Labs documentation to confirm specific package quantities and environmental compliance status. Ensure compatibility with system requirements before procurement. Contact the manufacturer directly for availability details regarding production units.
Select this component for designs requiring PCIe Gen-5 or CXL connectivity with extended reach capabilities. Consider the integrated AC-coupling and compact footprint for space-constrained applications like riser cards. Verify that the system supports the required HCSL clocking and bifurcation needs.
The PT5161LC belongs to the Aries Smart Retimer family designed for cloud-scale interconnects. It is pin- and register-compatible with other members of the portfolio, enabling easy performance scaling between CXL and PCIe Gen-4 and Gen-5 solutions within the same ecosystem.
PT5161LR serves as a PCIe 5.0 alternative. PT5161LX provides CXL/PCIe 5.0 functionality. PT4161LR offers PCIe 4.0 compatibility. All variants share the same physical footprint and pinout for direct substitution where protocol requirements align.
No, the device operates without requiring system software, relying on autonomous adaptation during normal operational link states.
It supports SRIS, SRNS, and common clock systems, utilizing a standard PCIe 100-MHz HCSL input clock.
The PT5161LC supports flexible link bifurcation, allowing it to operate as one x16 link, two x8 links, four x4 links, or eight x2 links.