PUMB1/DG/B3,115

Overview

The PUMB1/DG/B3,115 is a dual pre-biased NPN transistor array manufactured by Nexperia USA Inc. It integrates two NPN bipolar junction transistors with built-in biasing resistors in a compact surface-mount package. The device features a collector-emitter breakdown voltage of 50V and a maximum continuous collector current of 100mA. Each transistor includes an internal base resistor (R1) of 10 kΩ and an emitter resistor (R2) of 10 kΩ. The component is housed in a 6-TSSOP (SC-88/SOT-363) package, offering a maximum power dissipation of 300mW. It is designed for high-density circuit applications requiring simplified biasing networks.

Feature Summary

• Integrated dual NPN configuration with fixed internal biasing resistors to reduce external component count
• Compact 6-terminal surface-mount packaging suitable for space-constrained designs
• High DC current gain stability with specified minimum hFE at standard test conditions

Applications

• General-purpose switching circuits requiring simplified driver stages
• Logic level translation interfaces between microcontrollers and peripheral devices
• Low-power signal amplification stages in consumer electronics

Procurement Notes

Verify the specific suffix DG/B3 against official Nexperia documentation to confirm tape-and-reel specifications and lot traceability requirements. Ensure compatibility with automated pick-and-place equipment regarding the 6-TSSOP footprint dimensions. Cross-reference the manufacturer part number with authorized distributor catalogs to confirm current production status and RoHS compliance declarations prior to procurement.

Selection Notes

Select this component when a dual NPN pre-biased solution is required to minimize board space and assembly complexity. Compare the 10kΩ internal resistor values against the target logic family drive capabilities to ensure adequate base current. Evaluate the 300mW power dissipation limit against the expected thermal environment to maintain safe operating area margins during continuous operation.

Part Context

This part belongs to the Nexperia PUMB series of pre-biased bipolar transistors. These devices are engineered to replace discrete resistor-transistor combinations, thereby improving reliability and reducing manufacturing costs. The PUMB1 variant specifically denotes a dual NPN configuration, distinguishing it from PNP or mixed NPN/PNP counterparts within the same product family.

Replacement Considerations

Direct substitutes include other Nexperia dual NPN pre-biased transistors such as the PUMC11 or PUMD3 series, provided pinout compatibility and electrical parameters match. Verify that alternative packages maintain identical terminal assignments to prevent PCB redesign efforts.