SEARCH
— IC芯片 | 连接器 | 传感器 | 被动器件 —
The PUMB11,115 is a PNP/PNP double Resistor-Equipped Transistor (RET) manufactured by Nexperia USA Inc. It integrates two PNP transistors with built-in bias resistors in a TSSOP6 (SOT363-3) surface-mount package. Key electrical parameters include a collector-emitter voltage of -50 V and an output current capability of -100 mA per transistor. The device features a typical input bias resistor (R1) of 10 kΩ and a total power dissipation rating of 300 mW at 25 °C ambient temperature.
Verify the specific ordering suffix matches the required packaging format, such as tape and reel or cut tape, before placing orders. Confirm that the manufacturing site code aligns with project requirements. Ensure compliance with RoHS3 standards and check the latest product status documentation to confirm availability and production lifecycle stage prior to finalizing procurement plans.
Select this component when space constraints require a dual transistor solution in a SOT363-3 package. Verify that the 10 kΩ internal bias resistance meets the interface logic requirements. Ensure the thermal management strategy accounts for the 300 mW total power dissipation limit under expected operating conditions.
This part belongs to the PUMB series of PNP/PNP resistor-equipped double transistors. It serves as the PNP complement to the NPN/NPN PUMH11 and the NPN/PNP PUMD3 variants. All devices share the same SOT363-3 footprint but differ in internal transistor configurations and bias resistor values.
Direct functional replacements within the same family include PUMH11 (NPN/NPN) and PUMD3 (NPN/PNP), provided the polarity matches the circuit design. Verify pin compatibility and bias resistor values when substituting with other RET families.