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The Nexperia PUMB11,135 is a dual PNP resistor-equipped transistor (RET) housed in a TSSOP6 (SOT363-3) surface-mounted package. It integrates two PNP transistors with built-in bias resistors, where R1 is nominally 10 kΩ and the R2/R1 ratio is 1. The device supports a collector-emitter voltage of -50 V and a continuous output current of -100 mA per transistor. Total power dissipation is rated at 300 mW at 25 °C ambient temperature. Key electrical characteristics include a DC current gain (hFE) of at least 30 at -5 mA/-5 V, a saturation voltage of -100 mV maximum at -10 mA/-0.5 mA base current, and a transition frequency of 180 MHz typical.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm packaging details and manufacturing site codes. Ensure the procurement channel sources directly from authorized distributors or Nexperia to guarantee product authenticity and traceability. Confirm RoHS compliance status and lead times through official supply chain channels prior to finalizing orders.
Select this component when a compact dual PNP solution with integrated biasing is required. Verify that the 10 kΩ input resistance aligns with the driving source impedance. Ensure the -50 V collector-emitter voltage rating exceeds the maximum circuit voltage. Check thermal requirements against the 300 mW total power dissipation limit under expected operating conditions.
The PUMB11 belongs to Nexperia's family of PNP/PNP resistor-equipped double transistors. It serves as the PNP complement to the NPN/NPN PUMH11 and the NPN/PNP PUMD3. All devices share similar form factors and integration benefits but differ in transistor polarity and specific resistor values.
Direct replacements within the same polarity and configuration include the PUMH11 (NPN/NPN) and PUMD3 (NPN/PNP). Cross-polarity replacements require circuit redesign. Verify pinout compatibility and resistor values before substituting.