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The Nexperia PUMB17,115 is a dual PNP resistor-equipped transistor housed in a SOT363 (SC-88) plastic surface-mounted package. It integrates two PNP transistors with built-in bias resistors to simplify circuit design and reduce component count. The device features a collector-emitter voltage of -50 V and a DC output current of -100 mA per transistor. Total power dissipation is rated at 300 mW for the device and 200 mW per transistor at 25 °C ambient temperature. The typical input bias resistor R1 is 47 kΩ, with a resistor ratio (R2/R1) of 0.47.
Verify the specific ordering suffix against the manufacturer's current catalog to confirm packing method and manufacturing origin. The standard -115 suffix indicates tape and reel packaging. Confirm RoHS compliance status and product lifecycle stage via official Nexperia channels before finalizing procurement plans.
Select this component when space-saving dual PNP configurations are required. Ensure the -50 V voltage rating and -100 mA current limits meet the application demands. Verify that the integrated 47 kΩ input resistor aligns with the driving logic levels and desired switching speeds.
The PUMB17 belongs to the PEMB17/PUMB17 family of PNP/PNP resistor-equipped transistors. It serves as the SC-88 packaged variant, complementing the PEMD17 and PEMH17 models which utilize different package types. This series is designed to consolidate discrete transistor functions into a single compact footprint.
Direct functional equivalents include the PEMD17 and PEMH17 from the same family, though these utilize different packages. Cross-package replacements require careful verification of pinout compatibility and thermal performance characteristics.