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The PUMD10-Q is a 50 V, 100 mA NPN/PNP resistor-equipped double transistor (RET) housed in a SOT363-3 (SC-88) TSSOP6 surface-mounted package. It integrates an NPN transistor with a built-in bias resistor R1 of 2.2 kΩ and a general-purpose PNP transistor. The device features a collector-emitter voltage (VCEO) of 50 V, an output current (IO) of 100 mA, and a total power dissipation (Ptot) of 300 mW at 25 °C. The typical DC current gain (hFE) is 100 at IC = 10 mA and VCE = 5 V. The transition frequency (fT) reaches 230 MHz for the NPN section and 180 MHz for the PNP section.
Verify the specific suffix 'QH' against official Nexperia documentation, as the provided datasheet specifies 'PUMD10-Q'. Confirm that the ordering code matches the SOT363-3 package version released on July 20, 2026. Ensure compliance with automotive qualification requirements if used in vehicle systems.
Select this component when a compact NPN/PNP pair with integrated base biasing is required. The 2.2 kΩ input resistor simplifies drive circuits. Verify thermal constraints, as total power dissipation is limited to 300 mW. Consider the SOT363-3 footprint dimensions for PCB layout compatibility.
The PUMD10-Q belongs to Nexperia's Resistor-Equipped Transistor (RET) family. It serves as the NPN/PNP complement to the PUMB10-Q (PNP/PNP) and PUMH10-Q (NPN/NPN). This series is designed to replace discrete transistor pairs in space-constrained digital logic and switching applications.
Publicly confirmed substitutes include the PUMD10 (non-automotive grade) and the NHUMD10. Verify pinout compatibility and electrical parameters before substitution.