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The Nexperia PUMD10-Q is a dual Resistor-Equipped Transistor (RET) containing one NPN and one PNP transistor in a SOT363-3 package. It features built-in bias resistors with R1 at 2.2 kΩ and an R2/R1 ratio of 21. The device supports a collector-emitter voltage of 50 V and an output current of 100 mA per transistor. Total power dissipation is rated at 300 mW, with a junction temperature limit of 150 °C. It is qualified according to AEC-Q101 for automotive applications.
Verify the specific ordering suffix matches the required packaging configuration before purchase. Confirm that the SOT363-3 package variant aligns with the PCB footprint requirements. Ensure the AEC-Q101 qualification status meets the target application's reliability standards. Check the most recent datasheet revision for any updates to pinning or electrical characteristics.
Select this component when space constraints require integrating both NPN and PNP functions into a single surface-mount package. The fixed 2.2 kΩ input resistor value dictates the base drive requirements for the intended load. Verify that the 50 V breakdown voltage exceeds the maximum operating voltage of the circuit. Consider the thermal resistance values if multiple devices are mounted closely on the PCB.
The PUMD10-Q belongs to the PUMD series of dual resistor-equipped transistors. It serves as the complement to the PUMB10-Q (PNP/PNP) and PUMH10-Q (NPN/NPN). This family is designed to replace discrete transistor pairs, reducing board space and assembly complexity in digital logic and switching circuits.
Direct functional equivalents include the PUMB10-Q for PNP/PNP configurations and the PUMH10-Q for NPN/NPN configurations. Non-dual alternatives like the PUMF11 combine a resistor-equipped transistor with a general-purpose transistor.