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The Nexperia PUMD10/ZLF is a dual Resistor-Equipped Transistor (RET) featuring one NPN and one PNP transistor in a SOT363-3 (TSSOP6) package. It provides a collector-emitter voltage of 50 V and an output current capability of 100 mA per transistor. The device integrates bias resistors with a nominal value of 2.2 kΩ for R1 and a ratio of 21 for R2/R1. Total power dissipation reaches 300 mW at 25 °C ambient temperature, with junction temperatures supported up to 150 °C. Transition frequencies are specified at 230 MHz for the NPN section and 180 MHz for the PNP section.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm the exact tape and reel configuration or cut tape format intended for your assembly line. Confirm RoHS compliance status and moisture sensitivity level requirements prior to finalizing procurement orders to ensure compatibility with your manufacturing processes.
Select this component when space constraints require combining two discrete transistors into a single surface-mount footprint. Ensure the required base resistance values align with the fixed internal resistor specifications. Verify that the 50 V breakdown voltage and 100 mA current limits meet the operational demands of the target application circuit.
This part belongs to the PUMD10 family of NPN/PNP resistor-equipped double transistors manufactured by Nexperia. Complementary variants include the PUMB10 for PNP/PNP configurations and the PUMH10 for NPN/NPN setups. All share similar electrical characteristics and package dimensions within the SOT363-3 form factor.
Publicly confirmed substitute part numbers are not available in the provided source material.