PUMD10/ZLX

Overview

The Nexperia PUMD10 is a dual Resistor-Equipped Transistor (RET) containing one NPN and one PNP transistor in a TSSOP6 (SOT363-3) package. It features built-in bias resistors with R1 at 2.2 kΩ and an R2/R1 ratio of 21. The device supports a collector-emitter voltage of 50 V and an output current of 100 mA per transistor. Total power dissipation is rated at 300 mW, with a junction temperature limit of 150 °C. Transition frequencies are 230 MHz for the NPN section and 180 MHz for the PNP section.

Feature Summary

• Integrates NPN and PNP transistors with built-in bias resistors to simplify circuit design
• Reduces component count and pick-and-place costs compared to discrete solutions
• Provides high DC current gain of 100 at 10 mA collector current

Applications

• Low current peripheral driver
• Control of IC inputs
• Replaces general-purpose transistors in digital applications

Procurement Notes

Verify the specific ordering suffix against the manufacturer's official documentation to confirm packaging details such as reel size or tape type. Confirm RoHS compliance status and moisture sensitivity level requirements before finalizing procurement orders for production integration.

Selection Notes

Select this component when space constraints require a dual transistor solution with integrated base biasing. Ensure the required input resistance matches the fixed 2.2 kΩ value. Verify that the 50 V breakdown voltage and 100 mA current limits meet the specific application load requirements.

Part Context

This part belongs to the Nexperia PUMD series of resistor-equipped double transistors. Complementary configurations include the PUMB10 (PNP/PNP) and PUMH10 (NPN/NPN). The device utilizes the SOT363-3 plastic surface-mounted package for compact PCB implementation.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided source material.