PUMD10,125

Overview

The PUMD10,125 is a dual Resistor-Equipped Transistor (RET) containing one NPN and one PNP transistor in a TSSOP6 (SOT363-3) package. It features built-in bias resistors with R1 = 2.2 kΩ and R2 = 47 kΩ. The device supports a collector-emitter voltage of 50 V and an output current of 100 mA per transistor. Total power dissipation is limited to 200 mW per transistor and 300 mW for the entire device at 25 °C ambient temperature. The junction temperature range extends from -65 °C to 150 °C.

Feature Summary

• Integrates NPN and PNP transistors with built-in bias resistors to reduce component count
• Provides simplified circuit design by eliminating external base resistors
• Reduces pick and place costs through compact surface-mount packaging

Applications

• Low current peripheral driver
• Control of IC inputs
• Replaces general-purpose transistors in digital applications

Procurement Notes

Verify the specific ordering suffix matches the required tape and reel quantity. Confirm the package version corresponds to SOT363-3 as specified in the latest product data sheet revision. Ensure the manufacturing site code aligns with project requirements before finalizing procurement orders.

Selection Notes

Select this component when a complementary NPN/PNP pair with fixed biasing is required in a small footprint. Verify that the 2.2 kΩ input resistor and 47 kΩ emitter resistor values suit the target logic levels. Check thermal derating curves if operating near maximum power dissipation limits.

Part Context

This part belongs to the Nexperia PUMD10 family of double Resistor-Equipped Transistors. It serves as the NPN/PNP complement to the PUMB10 (PNP/PNP) and PUMH10 (NPN/NPN) variants. The device utilizes the SOT363-3 plastic surface-mounted package for space-constrained designs.

Replacement Considerations

• MUN5335DW1T1G
• DCX123JU-7-F