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The Nexperia PUMD12/DG/B3,115 is a dual Resistor-Equipped Transistor (RET) containing an NPN and a PNP transistor in a SOT363 (SC-88) surface-mount package. It features built-in bias resistors with R1 = 47 kΩ and R2 = 47 kΩ. The device supports a maximum collector-emitter voltage (VCEO) of 50 V and a continuous output current of 100 mA per transistor. Total power dissipation is rated at 200 mW per transistor and 300 mW for the device at 25°C ambient temperature. It operates within a junction temperature range of -65°C to +150°C and is qualified under AEC-Q101 standards.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm the exact packing method and reel specifications. Confirm that the requested part number matches the required SOT363 package variant and that all relevant compliance certifications are current for the intended deployment region.
Select this component when space-constrained designs require both NPN and PNP switching capabilities with fixed biasing. Ensure the application voltage does not exceed the 50 V limit and that the total power dissipation constraints are respected during thermal analysis. Verify compatibility with reflow soldering processes as specified in the datasheet.
This component belongs to the PEMD12/PUMD12 family of resistor-equipped transistors. The PUMD12 variant specifically utilizes the SOT363 (SC-88) package, distinguishing it from the PEMD12 which uses the SOT666 package. Both share identical electrical characteristics but differ in physical footprint and pin configuration.
Direct functional equivalents include the PEMD12 (SOT666 package) and other RETs with similar 47kΩ/47kΩ bias ratios and 50V ratings. Verify pinout compatibility and thermal resistance differences before substituting.