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The Nexperia PUMD12/ZLX is a dual Resistor-Equipped Transistor (RET) featuring one NPN and one PNP transistor in an SOT363 (SC-88) surface-mount package. It provides a maximum collector-emitter voltage of 50 V and an output current capability of 100 mA per transistor. The device integrates bias resistors R1 and R2, both typically valued at 47 kΩ, with a ratio range of 0.8 to 1.2. Total power dissipation is rated at 200 mW per transistor and 300 mW for the device at 25°C ambient temperature. Transition frequencies reach 230 MHz for the NPN and 180 MHz for the PNP element.
Verify the specific suffix ZLX against official ordering tables to confirm packaging details such as tape width and reel configuration. Confirm RoHS compliance status and REACH SVHC declarations prior to integration. Ensure the marking code D*1 aligns with manufacturing site requirements for traceability.
Select this RET when space constraints prevent discrete resistor placement or when simplified biasing is required for digital switching. Compare thermal resistance values against PCB copper area availability. Verify that the 50 V rating accommodates peak signal voltages and that the 100 mA limit suits the load requirements.
The PUMD12 belongs to the PEMD12/PUMD12 family of NPN/PNP resistor-equipped transistors. It shares electrical characteristics with the PEMD12 but utilizes the smaller SOT363 package instead of the SOT666. This family replaces general-purpose transistors in digital applications to streamline assembly processes.
Publicly confirmed substitutes include the PUMD10 and PUMD3 from the same manufacturer series. Verify pin compatibility and resistor tolerance specifications before substitution.
Both R1 (input) and R2 have a typical value of 47 kΩ, with a specified range of 33 kΩ to 61 kΩ.
Yes, the product is qualified in accordance with the AEC-Q101 standard for discrete semiconductors.
Reflow soldering is the only recommended soldering method for this device.