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The Nexperia PUMD12,135 is a dual Resistor-Equipped Transistor (RET) containing one NPN and one PNP transistor in a SOT363 (SC-88) surface-mount package. It features built-in bias resistors with nominal values of R1 = 47 kΩ and R2 = 47 kΩ. The device supports a maximum collector-emitter voltage (VCEO) of 50 V and an output current (IO) of 100 mA per transistor. Total power dissipation is rated at 200 mW per transistor and 300 mW per device at 25°C ambient temperature. Transition frequencies are specified at 230 MHz for the NPN and 180 MHz for the PNP transistor.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm the correct packing method and tape-and-reel specifications. Ensure that the selected variant matches the required surface-mount footprint dimensions and soldering profile constraints defined in the product data sheet.
Select this component when space-constrained designs require both NPN and PNP switching capabilities within a single compact package. The integrated 47 kΩ bias resistors eliminate external components, making it suitable for high-density PCB layouts where standard discrete transistor pairs would exceed available board area.
The PUMD12 belongs to the PEMD/PUMD family of resistor-equipped transistors manufactured by Nexperia. While the PEMD12 utilizes the SOT666 package, the PUMD12 specifically employs the SOT363 (SC-88) package. Both variants share identical electrical characteristics and pin configurations, differing primarily in physical package dimensions.
Publicly confirmed substitute part numbers for the PUMD12 are not provided in the verified source material.