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The Nexperia PUMD13-Q is an NPN/PNP Resistor-Equipped Transistor (RET) housed in a SOT363-3 (TSSOP6) surface-mount package. It integrates two transistors with built-in bias resistors, specifically R1 = 4.7 kΩ and R2 = 47 kΩ. The device supports a maximum collector-emitter voltage of 50 V and an output current of 100 mA per transistor. Total power dissipation is rated at 300 mW for the device and 200 mW per transistor at 25 °C ambient temperature. The component operates within a junction temperature range of -65 °C to 150 °C and features transition frequencies of 230 MHz for the NPN section and 180 MHz for the PNP section.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm packaging details and manufacturing site codes. Ensure that the selected variant matches the required AEC-Q101 qualification status if intended for automotive use. Cross-reference the marking code '3%' with production records to validate authenticity and traceability during the sourcing process.
Select this component when space constraints require a dual-transistor solution with integrated biasing. The SOT363-3 package offers a compact footprint suitable for high-density PCB layouts. Consider the 50 V breakdown voltage and 100 mA current limits to ensure compatibility with the target signal levels and load requirements in the specific application circuit.
The PUMD13-Q belongs to the PUMD series of resistor-equipped double transistors from Nexperia. This series is designed to replace discrete transistor pairs in digital logic circuits. The '-Q' suffix typically denotes automotive-grade qualification, aligning with the AEC-Q101 standard mentioned in the product data sheet for enhanced reliability in demanding environments.
PUMD13/1F